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M48Z129Y* M48Z129V
5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY BACK-UP MODE) BATTERY LOW PIN - PROVIDES WARNING OF BATTERY END-OF-LIFE AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z129Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - M48Z129V: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V SELF-CONTAINED BATTERY IN THE CAPHATTM DIP PACKAGE PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs
Figure 1. 32-pin PMDIP Module
32 1
PMDIP32 (PM) Module
* Contact local ST sales office for availability.
March 2005 1/16
M48Z129Y*, M48Z129V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 6 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12.PMDIP32 - 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. PMDIP32 - 32-pin Plastic DIP, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z129Y*, M48Z129V
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z129Y*, M48Z129V
SUMMARY DESCRIPTION
The M48Z129Y/V ZEROPOWER(R) SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32-pin DIP Module. The M48Z129Y/V directly replaces industry standard 128K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A16 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Reset Output (Open Drain) Battery Low Output (Open Drain) Supply Voltage Ground
17 A0-A16 W E G M48Z129Y M48Z129V
8 DQ0-DQ7
E G
RST BL
W RST BL VCC
VSS
AI02309
VSS
Figure 3. DIP Connections
RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 3 30 4 29 28 5 27 6 7 26 8 M48Z129Y 25 9 M48Z129V 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI02310
VCC A15 BL W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48Z129Y*, M48Z129V
Figure 4. Block Diagram
VCC A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E
W G
INTERNAL BATTERY
RST
BL
VSS
AI03608
OPERATION MODES
The M48Z129Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing data security in Table 2. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 4.5 to 5.5V or 3.0to 3.6V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data until valid power is restored.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 12 for details.
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M48Z129Y*, M48Z129V
READ Mode The M48Z129Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access.
Figure 5. Address Controlled, READ Mode AC Waveforms
tAVAV A0-A16 tAVQV tAXQX DQ0-DQ7 DATA VALID DATA VALID VALID
AI02324
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
VALID tAXQX tEHQZ
tGHQZ
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M48Z129Y*, M48Z129V
Table 3. READ Mode AC Characteristics
M48Z129Y Symbol Parameter
(1)
M48Z129V -85 Unit Max ns 85 85 45 5 5 ns ns ns ns ns 40 25 5 ns ns ns
-70 Min Max Min 85 70 70 35 5 3 30 20 5
tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 10., page 11).
WRITE Mode The M48Z129Y/V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable) are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveform
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02382
tWHAX
tWHQX
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M48Z129Y*, M48Z129V
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tWLWH tAVWL W tELEH tEHAX
tDVEH DQ0-DQ7 DATA INPUT
tEHDX
AI03611
Table 4. WRITE Mode AC Characteristics
M48Z129Y Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH tAVEH tWHQX(2,3) WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 75 75 5 -70 Max Min 85 0 0 65 75 5 15 35 35 0 15 30 M48Z129V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 10., page 11). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48Z129Y*, M48Z129V
Data Retention Mode With valid VCC applied, the M48Z129Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "Don't care". Note: A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z129Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO , the control circuit switches power to the internal battery, preserving data. The internal energy source will maintain data in the M48Z129Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 9.) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z129Y*, M48Z129V
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 5. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). No preheat above 150C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M48Z129Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5
M48Z129V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5
Unit V C pF ns V V
10/16
M48Z129Y*, M48Z129V
Figure 10. AC Testing Load Circuit
DEVICE UNDER TEST
650
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
Note: 1. 50pF for M48Z129V (3.3V).
Table 7. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
Table 8. DC Characteristics
M48Z129Y Sym Parameter Test Condition(1) Min ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 -70 Max 1 1 95 7 4 0.8 VCC + 0.3 0.4 2.2 -0.3 2.2 Min M48Z129V -85 Max 1 1 50 4 3 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
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M48Z129Y*, M48Z129V
Figure 11. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWPT E
RECOGNIZED
tDR tRB
tR tREC
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
RST
AI03610
Table 9. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tWPT tREC Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time M48Z129Y Write Protect Time M48Z129V VPFD (max) to RST High 40 40 250 200 ms M48Z129Y M48Z129V Min 300 10 s 150 10 1 40 150 s s s Max Unit s
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD Parameter(1,2) M48Z129Y Power-fail Deselect Voltage M48Z129V M48Z129Y VSO tDR(3) Battery Back-up Switchover Voltage M48Z129V Expected Data Retention Time 10 2.45 V YEARS 2.7 2.9 3.0 3.0 V V Min 4.2 Typ 4.35 Max 4.5 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 3. At 25C, VCC = 0V.
12/16
M48Z129Y*, M48Z129V
PACKAGE MECHANICAL INFORMATION
Figure 12. PMDIP32 - 32-pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 11. PMDIP32 - 32-pin Plastic DIP, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
13/16
M48Z129Y*, M48Z129V
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M48Z 129Y -70 PM 1 TR
Device Type M48Z
Supply Voltage and Write Protect Voltage 129Y(1) = VCC = 4.5 to 5.5V; 4.2V VPFD 4.5V 129V = VCC = 3.0 to 3.6V; 2.7V VPFD 3.0V
Speed -70 = 70ns (M48Z129Y) -85 = 85ns (M48Z129V)
Package PM = PMDIP32
Temperature Range 1 = 0 to 70C
Shipping Method blank = Tubes TR = Tape & Reel
Note: 1. Contact Local Sales Office
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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M48Z129Y*, M48Z129V
REVISION HISTORY
Table 13. Document Revision History
Date December 1999 30-Mar-00 20-Jun-00 14-Sep-01 29-May-02 02-Apr-03 18-Feb-05 Version 1.0 2.0 2.1 3.0 3.1 4.0 5.0 First Issue From Preliminary Data to Data Sheet tGLQX changed for M48Z129Y (Table 3) Reformatted; Temperature information added to tables (Table 7, 8, 3, 4, 9, 10) Add countries to disclaimer v2.2 template applied; test condition updated (Table 10) Reformatted; IR reflow update (Table 5) Revision Details
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M48Z129Y*, M48Z129V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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